Résumé
:
Mise à jour
prochaine
Domaine d'activité :
Mise à jour prochaine
Publications :
Revues internationales :
A.
Fonseca, E. de Foucauld, P. Lorenzini & G.
Jacquemod, «Low power
28nm FDSOI 2.45 GHz PLL», Journal of Low Power
Electronics,
vol. 10, n°
1, p. 149-162, 2014.
F. Duhem, N. Marques, F. Muller, H. Rabah, S. Weber
& P. Lorenzini, “Dynamically reconfigurable entropy coder for
multi-standrad video adaptation using FaRM”, Microprocessors and
Microsystems, vol. 37, pp. 1-8, 2013.
F. Duhem, F. Muller
& P. Lorenzini, “Reconfiguration time overhead on Field
Programmable Gate arrays: Reduction and cost model”, IET Comput.
Digital Tech, vol. 6, n°2, pp. 105-113, 2012.
P. Mazoyer, S. Puget, G. Bossu, P. Masson, P.
Lorenzini & J.M. Portal, “Thin film embedded memory solution”,
Current Applied Physics, vol. 10, n°1, pp. e9-e12, 2010.
S. Puget, G. Bossu, P.
Masson, P. Mazoyer, R. Ranica, A. Villaret, P. Lorenzini, J.M. Portal,
G. Ghibaudo, R. Bouchakour, G. Jacquemod & T. Skotnicki, “Modelling
the Independent Double Gate Transistor in Accumulation Regime for 1T
DRAM Application”, IEEE Trans. On Electron. Devices, vol. 57,
n°4, pp. 855-865, 2010.
Y. Cordier, F. Semond, J. Massies, M. Leroux, P.
Lorenzini & C. Chaix, “Developments for the production of high
quality and high uniformity AlGaN/GaN heterostructures by ammonia MBE”,
Journal of Crystal Growth, 301-302, pp. 434-436,
2007.
R. Tauk, J.
Lusakowski, W. Knap, A. Tiberj, Z. Bougrioua, M. Azize, P. Lorenzini,
M. Sakowicz, K. Karpierz, C. Fenouillet-Beranger, M. Casse, C. Gallon,
F. Boeuf & T. Skotnicki, “Low electron mobility of field-effect
transistor determined by modulated magnetoresistance”, Journal of
applied physics, vol. 102, 2007.
Conférences
"Invité" :
G.
Jacquemod, A. Fonseca, E. de
Foucauld,
Y. Leduc,
& P. Lorenzini, “2.45 GHz 0.8
mW VCRO in FDSOI 28
nm technology”, ICSS, Hong
Kong, China, pp. 74-75,
2014.
A.
Fonseca, G. Jacquemod, Y. Leduc, E. de
Foucauld & P. Lorenzini, “VCO
Design in SOI technologies”, NEWCAS, Special Session
«Frequency
synthesis – New designs, new technologies», Trois
Rivières, Canada, 2014.
G.
Jacquemod, A. Fonseca, Y. Leduc, E. de
Foucauld & P. Lorenzini, “Analog
Design in FDSOI 28
nm technology and
beyond”, CISIS, 3rd
Annual World Congress of Emerging InfoTech, Dalian, China, 2014.
A.
Fonseca, E. de
Foucauld, P. Lorenzini & G. Jacquemod, “CMOS
technology beyond 22 nm”, ICSS, Las Vegas, USA, pp. 152-153,
2013.
C. Jacquemod, A.
Chargui, K. Aguir, B. Nicolle & P. Lorenzini, “Miniaturized current
sensor for smart building application”, ICSS, Las Vegas, USA,
pp. 29-30,
2013
Conférences
internationales :
C.
Jacquemod, K. Aguir, B. Nicolle,
P. Lorenzini & G. Jacquemod, “Innovating
current
sensor for NILM application”, NILM Workshop, Austin, USA,
June 2014.
C.
Jacquemod, K. Aguir, B. Nicolle, P. Lorenzini & G. Jacquemod, “Innovationg
current sensor for smart building application”, Sensors, Energy
Harvesting, Wireless Network and Smart Object, SENSO, Aix en Provence, France, 2014.
A.
Fonseca, E. de Foucauld, P.
Lorenzini & G. Jacquemod, "Process
variation compensation for PLL on
FDSOI 28nm", VARI/PATMOS, Karlsruhe, Germany
2013.
C.
Jacquemod, K.
Nguyen Trung, A. Chargui, K. Aguir, O. Zammit, E. Dekneuvel, B.
Nicolle, P.
Lorenzini & G. Jacquemod, "Power Consumption Monitoring for
Smart Building Application", SAME,
University Booth, Sophia
Antipolis, 2013.
F. Duhem, F. Muller &
P. Lorenzini, “Transaction-level modeling of dynamically reconfigurable
systems using SystemC”, SAME, Sophia Antipolis, France, 2011.
F. Duhem, F. Muller & P. Lorenzini, “FaRM: Fast
Reconfiguration Manager for reducing reconfiguration time overhead on
FPGA”, ARC symposium, Belfast, UK, 2011.
F. Duhem, F. Muller
& P. Lorenzini, “Methodology for designing partially reconfigurable
systems using transaction-level modeling”, DASIP, Tampere,
Finland, 2011.
S. Puget, J.M. Portal, P. Masson, P. Mazoyer, G.
Bossu, P. Lorenzini, R. Bouchakour & T. Skotnicki, “Optimisation of
independent double gate loating body cell DRAM performance by
technology screening”, SiliconNano-Worshop, Kyoto, Japan, 2009.
S. Puget, G. Bossu, C.
Fenouillet-Beranger, P. Perreau, P. Masson, P. Lorenzini, P. Mazoyer,
J.M. Portal, R. Bouchakour & T. Skotnicki, “FDSOI floating body
cell eDRAM using gate-induced drain-leakage (GIDL) write current for
high speed and low power applications”, International Memory
Worshop, Monterey, USA, 2009.
